FPGA Design Seminars - Online

FDS 100, ispLEVER Basics

Intended for a new user or a user who uses ispLEVER infrequently. Lecture covers the landscape of tools available for FPGA design and describes the basics of operating the tools to transform a logic design modeled in Verilog HDL or VHDL into a programming bit-stream for the target device.

Rationale: This course offers a jump-start or a refresher on how to use ispLEVER software for FPGA design.

FDS 100 originally broadcast October 2, 2008.

FDS 101, Synplify/Pro Basics

Intended for new users or a user who uses Synplify/Pro FPGA Synthesis infrequently. Lecture covers project management, key optimization options, visualization features, constraints entry, and key output reports of the 'Synplify/Pro for Lattice' product license.

Rationale: This course offers a jump-start or a refresher on how to use Synplify for Lattice logic synthesis software.

FDS 101 originally broadcast September 4, 2008.

FDS 102, Active-HDL Basics

Intended for new users or a user who uses Active-HDL simulation infrequently. Lecture covers project management, design entry, debugging and visualization features, and back-end integration with ispLEVER tools for the 'Active-HDL Lattice Edition' product license.

Rationale: This course offers a jump-start or a refresher on how to use AHDL for simulation.

FDS 102 and 103 originally broadcast August 7, 2008.

FDS 103, Migrating from ModelSim to Active-HDL

Intended for users familiar with ModelSim adopting Active-HDL.

Rationale: This course offers advice on how to transition from the ModelSim verification environment to Active-HDL including: translating simulation project files, environment options, command scripts, compiler and simulator options, and legacy IP.

FDS 102 and 103 originally broadcast August 7, 2008.